1. Field of the Invention
The present invention relates to a cell string and a reading method for the cell string, and more particularly, to a cell string wherein a semiconductor body where a channel is formed includes at least two or more layers and adjacent layers are made of materials having different energy band gaps to increase a turn-on current, using positive feedback to obtain steep switching characteristic, and capable of reducing distribution of a turn-on voltage and a reading method for the cell string.
2. Description of the Related Art
Various researches have been made in order to improve a degree of integration and performance of a flash memory device.
A structure of a vertical-type TCAT flash memory cell string for improving the degree of integration is disclosed in “Vertical Cell Array Using TCAT (Tera Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory” (Jaehoon Jang, et al., 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 192-193) (referred to as Non-Patent Document 1).
FIGS. 1A and 1B are cross-sectional diagrams illustrating a vertical-type TCAT flash memory cell string in X and Y directions disclosed in Non-Patent Document 1. FIGS. 2A and 2B are graphs illustrating a voltage (control gate voltage Vg)−current (bit line current IBL) characteristic of the cell string and a distribution of threshold voltage (Vth) with respect to 32 cells of string. In FIGS. 1A and 1B, the aforementioned TCAT flash memory cell string includes a channel region which is formed in the vertical direction on a semiconductor substrate formed as a p− substrate, cell string which includes a plurality of cell devices which are formed in series to be electrically separated from each other and is formed at the side surface of the channel region, and an n+ region which is formed on the semiconductor substrate. The upper portion of the channel region is connected to bit lines BL, and gate electrodes of the cell devices are connected to word lines WL. As illustrated in FIG. 2B, the distribution of the threshold voltage of each cell device in the above-described TCAT flash memory cell string is as wide as 1 V or more.
In addition, a 3D NAND flash memory device having a dual-channel structure is disclosed in “A Novel Dual-Channel 3D NAND Flash Featuring both N-Channel and P-Channel NAND Characteristics for Bit-alterable Flash Memory and A New Opportunity in Sensing the Stored Charge in the WL Space” (Hang-Ting Lue, et al., 2013 IEEE pp. 3.7.1-3.7.4) (referred to as Non-Patent Document 2)
FIGS. 3A and 3B are conceptual diagrams illustrating the 3D NAND flash memory having a dual-gate structure disclosed in Non-Patent Document 2. FIG. 4 is a graph illustrating an Id-Vg characteristic curve of the flash memory.
In the flash memory devices in the related art illustrated in FIGS. 1A and 1B and FIGS. 3A and 3B, the slope is low in the range (sub-threshold) of lower than the threshold voltage Vth, and thus, the distribution of the threshold voltage Vth is wide. As a result, a refresh margin cannot be increased. By increasing the refresh margin, a read time can be shortened. In the range of less than the threshold voltage Vth, the slope of the I-V characteristic curve is as high as about 250 mV/dec. Because the slope of the I-V characteristic curve is very high in the gate structure of FIGS. 1A and 1B where a tubular channel and a gate insulating film stack formed thereon are surrounded and the dual-gate structure of FIGS. 2A and 2B, the distribution of the threshold voltage can be greatly increased. In particular, in the case where the slope in the sub-threshold range is deteriorated due to an increase in program/erase cycle or the like, the distribution of the threshold voltage can be more greatly increased.